Morgan McKinley Japan
NVM Memory Design Engineer - Semiconductor IP (Mie)
Competitive
Japanese Level: Level 1?
Non-Volatile MemoryMemory Circuit DesignSemiconductor IP
“Fluent Japanese and English required; 3+ years NVM/memory circuit design experience. No visa information provided.”
From the original job posting
About this role
Morgan McKinley Japan is hiring a NVM Memory Design Engineer - Semiconductor IP (Mie) in Japan. This is a Mid Level Engineering role. Japanese requirement: B2B Sales Japanese (business-level fluency for client-facing communication). Visa sponsorship may be available on a case-by-case basis. If you are looking for Engineering opportunities in Japan that welcome foreign professionals, this role at Morgan McKinley Japan could be a great fit. Apply directly through the link below.